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Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 147

UG111 (v1.4) January 30, 2004 1-800-255-7778

VHDL Peripheral Definitions

Entity-level VHDL Attributes for Automation Support

Table 8-2: Entity-level VHDL Attributes

Attribute Type Values Default

PsfUtil

Automation

Definition

ADDR_SLICE integer

X - Address slice of BRAM

controller

AWIDTH

integer -

X - Address width of

BRAM controller

ALERT

string -

X-Alert message

CORE_STATE

string

ACTIVE

DEPRECATED

OBSOLETE

DEVELOPMENT

ACTIVE - Core state

BUSID

string -

X - Bus Identifier string

for cores using the

optional <BI> as part

of the bus signal names

DWIDTH

integer -

X - Data width of BRAM

controller

HDL

string

BOTH

VERILOG

VHDL

VHDL Input

Language of

source

HDL design

availability.

IMP_NETLIST

string

TRUE

FALSE

FALSE TRUE Synthesize HDL to a

hardware

implementation netlist

IPTYPE

string

BRIDGE

BUS

BUS_ARBITER

PERIPHERAL

PROCESSOR

IP PERIPHERAL Type of component

IP_GROUP string LOGICORE

INFRASTRUCTURE

REFERENCE

ALLIANCE

USER

USER USER Defines the logical

grouping to which IP

belongs.

NUM_WRITE_ENAB

LES

integer -

X - Number of write

enables of BRAM

controller

1 2 ... 142 143 144 145 146 147 148 149 150 151 152 ... 345 346

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